SN74HC165-Q1 - 8-Bit Parallel-Load Shift Registers

The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH) output.

H) inputs that are enabled by a low level at the shift/load (SH/LD) inp

• a clock-inhibit (CLK INH) function and a complementary serial (QH) output. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel input.