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SN74LV125A - Quadruple Bus Buffer Gates

Description

The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.

Features

  • 2-V to 5.5-V VCC Operation.
  • Max tpd of 6 ns at 5 V.
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C.
  • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C.
  • Support Mixed-Mode Voltage Operation on All Ports.
  • Ioff Supports Partial-Power-Down Mode Operation.
  • Latch-Up Performance Exceeds 250 mA Per JESD 17.
  • ESD Protection Exceeds JESD 22.
  • 4000-V Human-Body Model.
  • 200-V Ma.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SN74LV125A SCES124O – DECEMBER 1997 – REVISED MAY 2022 SN74LV125A Quadruple Bus Buffer Gates With 3-State Outputs 1 Features • 2-V to 5.5-V VCC Operation • Max tpd of 6 ns at 5 V • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.
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