D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 14 ns
D ±4-mA Output Drive at 5 V
SN54HC42 . . . J OR W PACKAGE
SN74HC42 . . . D, N, OR NS PACKAGE
4ĆLINE TO 10ĆLINE DECODERS (1 of 10)
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003
D Low Input Current of 1 µA Max
D Full Decoding of Input Logic
D All Outputs Are High for Invalid BCD
D Also for Applications as 3-Line to 8-Line
SN54HC42 . . . FK PACKAGE
3 2 1 20 19
9 10 11 12 13
NC − No internal connection
These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected
in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic
ensures that all inputs remain off for all invalid input conditions.
PDIP − N
Tube of 25
Tube of 40
−40°C to 85°C SOIC − D
Reel of 2500
Reel of 250
SOP − NS
Reel of 2000 SN74HC42NSR
CDIP − J
Tube of 25
−55°C to 125°C CFP − W
Tube of 150
LCCC − FK
Tube of 55
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.