TMS320C6201
Overview
- 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency
- 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel
- 16-Bit Host-Port Interface (HPI) -- Access to Entire Memory Map
