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TMS320C6201 - FIXED-POINT DIGITAL SIGNAL PROCESSOR

Description

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Features

  • -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) -- Glueless Interface to Asynchronous Memories: SRAM and EPROM -- Glueless Interface to Synchronous.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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D High-Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6201 -- 5-ns Instruction Cycle Time -- 200-MHz Clock Rate -- Eight 32-Bit Instructions/Cycle -- 1600 MIPS D VelociTI™ Advanced Very Long Instruction Word (VLIW) TMS320C62x™ DSP CPU Core -- Eight Independent Functional Units: -- Six ALUs (32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Results) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional D Instruction Set Features -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization D 1M-Bit On-Chip SRAM -- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) -- 512K-Bit
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