TMS320C6204 Description
-- Six ALUs (32-/40-Bit) -- Two 16-Bit Multipliers (32-Bit Result) -- Load-Store Architecture With 32 32-Bit General-Purpose Registers -- Instruction Packing Reduces Code Size -- All Instructions Conditional D Instruction Set.
TMS320C6204 Key Features
- Byte-Addressable (8-, 16-, 32-Bit Data) -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- B
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes) -- Organized as Two 32K-Byte Blocks for Improved Concurrency
- Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- 52M-Byte Addressable External Memory Space
- Glueless/Low-Glue Interface to Popular PCI Bridge Chips
- Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses
- Master/Slave Functionality -- Glueless Interface to Synchronous FIFOs
- CMOS Technology