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D High-Performance Fixed-Point Digital
Signal Processor (DSP) − TMS320C6205 − 5-ns Instruction Cycle Time − 200-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600 MIPS
D VelociTI Advanced-Very-Long-Instruction-
Word (VLIW) TMS320C62x DSP Core − Eight Highly Independent Functional
Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Result) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional
D Instruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization
D 1M-Bit On-Chip SRAM
− 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
− 512K-Bit Dual-Access Internal Data (64K Bytes