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TMS626162 Datasheet Preview

TMS626162 Datasheet

DYNAMIC RANDOM-ACCESS MEMORIES

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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
D Organization . . . 512K × 16 × 2 Banks
D 3.3-V Power Supply (± 10% Tolerance)
D Two Banks for On-Chip Interleaving
(Gapless Accesses)
D High Bandwidth – Up to 83-MHz Data Rates
D CAS Latency (CL) Programmable to 2 or 3
Cycles From Column-Address Entry
D Burst Sequence Programmable to Serial or
Interleave
D Burst Length Programmable to 1, 2, 4, 8, or
Full Page
D Chip Select and Clock Enable for
Enhanced-System Interfacing
D Cycle-by-Cycle DQ-Bus Mask Capability
With Upper and Lower Byte Control
D Auto-Refresh and Self-Refresh Capability
D 4K Refresh (Total for Both Banks)
D High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
D Power-Down Mode
D Compatible With JEDEC Standards
D Pipeline Architecture
D Temperature Ranges:
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
DGE PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
DQML
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 VSS
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VCCQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VCCQ
37 NC
36 DQMU
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
SYNCHRONOUS
CLOCK CYLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
tCK3
tCK2
tAC3
tAC2
(CL‡ = 3) (CL = 2) (CL = 3) (CL = 2)
’626162-12A† 12 ns
15 ns
9 ns
9 ns
’626162-12
12 ns 18 ns 9 ns 10 ns
–12A speed device is supported only at –5/+10% VCC
CL = CAS latency
REFRESH
INTERVAL
tREF
64 ms
64 ms
description
The TMS626162 device is a high-speed
16 777 216-bit synchronous dynamic random-
access memory (SDRAM) organized as two
banks of 524 288 words with 16 bits per word.
All inputs and outputs of the TMS626162 series
are compatible with the LVTTL interface.
PIN NOMENCLATURE
A0–A10
A11
CAS
CKE
CLK
CS
DQ0–DQ15
DQML, DQMU
NC
RAS
VCC
VCCQ
VSS
VSSQ
W
Address Inputs
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
System Clock
Chip Select
SDRAM Data Input/Output
Data/Output Mask Enables
No Connect
Row-Address Strobe
Power Supply (3.3-V Typ)
Power Supply for Output Drivers (3.3-V Typ)
Ground
Ground for Output Drivers
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1




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TMS626162 Datasheet Preview

TMS626162 Datasheet

DYNAMIC RANDOM-ACCESS MEMORIES

No Preview Available !

TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed
microprocessors and caches.
The TMS626162 SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).
functional block diagram
CLK
CKE
CS
DQMx
RAS
CAS
W
A0 – A11
AND
12
Control
Array Bank T
Array Bank B
DQ
Buffer
DQ0 – DQ15
16
Mode Register
operation
All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0– DQ15, also are referenced to the rising edge of CLK. The ’626162 has two banks that are accessed
independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles
refresh both banks alternately.
Five basic commands or functions control most operations of the ’626162:
D Bank activate/row-address entry
D Column-address entry/write operation
D Column-address entry/read operation
D Bank deactivate
D Auto-refresh
D Self-refresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select / deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’626162. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443


Part Number TMS626162
Description DYNAMIC RANDOM-ACCESS MEMORIES
Maker etcTI
Total Page 30 Pages
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