TMS626812 Datasheet | Texas Instruments

description The TMS626812 is a high-speed 16 777 216-bit synchronous dynamic random access memory (SDRAM) device organized as two banks of 1 048 576 words with eight bits per word. All inputs and outputs of the TMS626812 series are patible with the LVTTL interface. PIN NOMENCLATURE A0 - A10 Address Inputs A0 - A10 Row Addresses A0 - A8 Column Addresses A10 Automatic-Precharge Select A11 Bank Select CAS Column-Address Strobe CKE Clock Enable CLK System Clock CS Chip Select DQ0 - DQ7 SDRAM Data Input / Output DQM Data / Output Mask Enable NC No External Connect RAS Row-Address Strobe VCC VCCQ VSS VSSQ W Power Supply (3.3-V Typ) Power Supply for Output Drivers (3.3-V Typ) Ground Ground for Output Drivers Write Enable Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997, Texas Instruments Incorporated - POST OFFICE BOX 1443 HOUSTON, TEXAS 77251- 1443 TMS626812 1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS687A - JULY 1996 - REVISED APRIL 1997 description (continued) The SDRAM employs state-of-the-art technology for high performance,...