TMS626812A Datasheet | Texas Instruments

2A is a high-speed, 16777 216-bit synchronous dynamic random-access memory (SDRAM) device organized as: D Two banks of 1 048 576 words with 8 bits per word TMS626812A DGE PACKAGE ( TOP VIEW ) VCC DQ0 VSSQ DQ1 VCCQ DQ2 VSSQ DQ3 VCCQ NC NC W CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 VSS 43 DQ7 42 VSSQ 41 DQ6 40 VCCQ 39 DQ5 38 VSSQ 37 DQ4 36 VCCQ 35 NC 34 NC 33 DQM 32 CLK 31 CKE 30 NC 29 A9 28 A8 27 A7 26 A6 25 A5 24 A4 23 VSS A[0: 10] A11 CAS CKE CLK CS DQ[0:7] DQM NC RAS VCC VCCQ VSS VSSQ W PIN NOMENCLATURE Address Inputs A0 - A10 Row Addresses A0 - A8 Column Addresses A10 Automatic-Precharge Select Bank Select Column-Address Strobe Clock Enable System Clock Chip Select SDRAM Data Input / Output Data-Input / Data-Output Mask Enable No External Connect Row-Address Strobe Power Supply (3.3-V Typical) Power Supply for Output Drivers (3.3-V Typical) Ground Ground for Output Drivers Write Enable Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1998, Texas Instruments Incorporated - POST OFFICE BOX 1443 HOUSTON, TEXAS 77251- 1443 TMS626812A 1 048 576 BY 8ĆBIT BY 2ĆBANK SYNCHRONOUS DYNAMIC RANDOMĆACCESS MEMORY SMOS691B - JULY 1997 - REVISED APRIL 1998 description (continued) All inputs and outputs of the TMS626812A series are patible with the LVTTL interface. The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and...