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TPIC5303 - power DMOS array

General Description

SOURCE2 4 GATE2 5 13 DRAIN1 12 DRAIN1 The TPIC5303 is a monolithic gate-protected power DMOS array that consists of three independent electrically isolated N-channel DRAIN3 DRAIN3 GND 6 7 8 11 SOURCE3 10 SOURCE3 9 GATE3 enhancement-mode DMOS transistors.

Each transistor

Overview

ą TPIC5303 3ĆCHANNEL INDEPENDENT GATEĆPROTECTED POWER DMOS ARRAY SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995 • Low rDS(on) .

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Key Features

  • integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor. The TPIC5303 is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized for operation over the case temperature range of.
  • 40°C to 125°C. schematic DRAIN1 12, 13 GATE2.