74AHC273 Datasheet | Nexperia

description The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A. The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The mon clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input. The device is useful for applications where only the true output is required and the clock and master reset are mon to all storage elements. 2. Features - Balanced propagation delays - All inputs have Schmitt-trigger actions - Inputs accept voltages higher than VCC - Ideal buffer for MOS microcontroller or memory - mon clock and master reset - Input levels: - For 74AHC273: CMOS level - For 74AHCT273: TTL level - ESD protection: - HBM JESD22-A114E exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - CDM JESD22-C101C exceeds 1000 V - Multiple package options - Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74AHC273D 74AHCT273D -40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74AHC273PW 74AHCT273PW -40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm 74AHC273BQ 74AHCT273BQ -40 °C to +125 °C DHVQFN20 plastic dual in-line patible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm Version SOT163-1 SOT360-1 SOT764-1 Nexperia 4. Functional diagram 3 D0 Q0...