74AHCT74-Q100 Description
74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-Power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD).
74AHCT74-Q100 Key Features
- Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accept voltages higher than VCC
- Input levels
- For 74AHC74-Q100: CMOS level
- For 74AHCT74-Q100: TTL level
- ESD protection
- MIL-STD-883, method 3015 exceeds 2000 V
74AHCT74-Q100 Applications
- Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C