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74ALVC32PW - Quad 2-input OR gate

Download the 74ALVC32PW datasheet PDF. This datasheet also covers the 74ALVC32 variant, as both devices belong to the same quad 2-input or gate family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74ALVC32 is a quad 2-input OR gate.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

2.

Key Features

  • Wide supply voltage range from 1.65 V to 3.6 V.
  • 3.6 V tolerant inputs/outputs.
  • CMOS low power consumption.
  • Direct interface with TTL levels (2.7 V to 3.6 V).
  • Power-down mode.
  • Latch-up performance exceeds 250 mA.
  • Complies with JEDEC standards:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74ALVC32-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVC32 Low Voltage Quad 2-Input OR Gate Fairchild Semiconductor
74ALVC32 Quad 2-input OR gate NXP
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74ALVC374 Octal D-type flip-flop positive edge-trigger NXP
74ALVC38 Low Voltage Quad 2-Input NAND Gate Fairchild Semiconductor

Other Datasheets by Nexperia

Part Number Description
74ALVC32 Quad 2-input OR gate
74ALVC32-Q100 Quad 2-input OR gate
74ALVC32BQ Quad 2-input OR gate
74ALVC32D Quad 2-input OR gate
74ALVC373 Octal D-type transparent latch

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74ALVC32 Quad 2-input OR gate Rev. 5 — 30 April 2021 Product data sheet 1. General description The 74ALVC32 is a quad 2-input OR gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. 2. Features and benefits • Wide supply voltage range from 1.65 V to 3.6 V • 3.6 V tolerant inputs/outputs • CMOS low power consumption • Direct interface with TTL levels (2.7 V to 3.6 V) • Power-down mode • Latch-up performance exceeds 250 mA • Complies with JEDEC standards: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8B (2.7 V to 3.6 V) • ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C 3. Ordering information Table 1.