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74ALVC32D Datasheet Preview

74ALVC32D Datasheet

Quad 2-input OR gate

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74ALVC32
Quad 2-input OR gate
Rev. 4 — 28 September 2020
Product data sheet
1. General description
The 74ALVC32 is a quad 2-input OR gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74ALVC32D
-40 °C to +85 °C
74ALVC32PW
-40 °C to +85 °C
74ALVC32BQ
-40 °C to +85 °C
Name
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1




nexperia

74ALVC32D Datasheet Preview

74ALVC32D Datasheet

Quad 2-input OR gate

No Preview Available !

Nexperia
4. Functional diagram
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
Fig. 1. Logic symbol
1Y 3
2Y 6
3Y 8
4Y 11
mna242
A
B
Fig. 3. Logic diagram (one gate)
5. Pinning information
5.1. Pinning
74ALVC32
1A 1
14 VCC
1B 2
13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
8 3Y
aaa-032403
Fig. 4. Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
74ALVC32
Quad 2-input OR gate
1
≥1
3
2
4
≥1
6
5
9
≥1
8
10
12
≥1
11
13
Fig. 2. IEC logic symbol
mna243
Y
mna241
74ALVC32
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
aaa-032404
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND
Fig. 5. Pin configuration SOT762-1 (DHVQFN14)
74ALVC32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 28 September 2020
© Nexperia B.V. 2020. All rights reserved
2 / 12


Part Number 74ALVC32D
Description Quad 2-input OR gate
Maker nexperia
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74ALVC32D Datasheet PDF






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