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74HC10 Datasheet Preview

74HC10 Datasheet

Triple 3-input NAND gate

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74HC10; 74HCT10
Triple 3-input NAND gate
Rev. 3 — 5 August 2016
Product data sheet
1. General description
The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For74HC10: CMOS level
For 74HCT10: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
Version
74HC10D
40 C to +125 C SO14
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCT10D
74HC10DB 40 C to +125 C
74HCT10DB
SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74HC10PW 40 C to +125 C
74HCT10PW
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1




nexperia

74HC10 Datasheet Preview

74HC10 Datasheet

Triple 3-input NAND gate

No Preview Available !

Nexperia
4. Functional diagram
74HC10; 74HCT10
Triple 3-input NAND gate
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PQD
Fig 1. Logic symbol

  


  


  

PQD
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
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PQD
Fig 3. Logic diagram (one gate)
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+&7
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DDD
Fig 4. Pin configuration SO14
5.2 Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A
1B, 2B, 3B
GND
1C, 2C, 3C
1Y, 2Y, 3Y
VCC
Pin
1, 3, 9
2, 4, 10
7
13, 5, 11
12, 6, 8
14
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+&7
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DDD
Fig 5. Pin configuration for (T)SSOP14
Description
data input
data input
ground (0 V)
data input
data output
supply voltage
74HC_HCT10
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 5 August 2016
© Nexperia B.V. 2017. All rights reserved
2 of 14


Part Number 74HC10
Description Triple 3-input NAND gate
Maker nexperia
Total Page 14 Pages
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