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74HCT138BQ - 3-to-8 line decoder/demultiplexer

This page provides the datasheet information for the 74HCT138BQ, a member of the 74HC138 3-to-8 line decoder/demultiplexer family.

Description

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

Features

  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Demultiplexing capability.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • Active LOW mutually exclusive outputs.
  • Input levels:.
  • For 74HC138: CMOS level.
  • For 74HCT138: TTL level.
  • Complies with JEDEC.

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Datasheet preview – 74HCT138BQ

Datasheet Details

Part number 74HCT138BQ
Manufacturer nexperia
File Size 269.86 KB
Description 3-to-8 line decoder/demultiplexer
Datasheet download datasheet 74HCT138BQ Datasheet
Additional preview pages of the 74HCT138BQ datasheet.

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Full PDF Text Transcription

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74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 9 — 13 August 2021 Product data sheet 1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes.
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