Description
A-Data Revision History Revision 1 ( Dec.2001 ) 1.Fister release.ADD8616A8A Revision 2 ( Apr.2002 ) 1.Changed module current specification.2.A.
The ADD8616A8A are four-bank Double Data Rate(DDR) Synchronous DRAMs organized as 4,194,304 words x 16 bits x 4 banks, Synchronous design allows preci.
Features
* 2.5V for VDDQ power supply
* SSTL_2 interface
* MRS Cycle with address key programs -CAS Latency (2, 2.5) -Burst Length (2,4 &8) -Burst Type (sequential & Interleave)
* 4 banks operation
* Differential clock input (CK, /CK) operation
* Double data rate int
