AVR201628

DDR2 SDRAM

AVR201628 Features

* VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V

* JEDEC-standard 1.8V I/O (SSTL_18-compatible)

* Differential data strobe (DQS, DQS#) option

* 4n-bit prefetch architecture

* Duplicate output strobe (RDQS) option for x8

* DLL to align DQ and DQS transitions wit

AVR201628 General Description

The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM e.

AVR201628 Datasheet (8.12 MB)