ATF1504ASL
Features
- High-density, High-performance, Electrically-erasable plex Programmable Logic Device ̶ 64 Macrocells ̶ 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell ̶ 44, 84, 100 Pins ̶ 7.5ns Maximum Pin-to-pin Delay ̶ Registered Operation up to 125MHz ̶ Enhanced Routing Resources
- In-System Programmability (ISP) via JTAG
- Flexible Logic Macrocell
̶ D/T/Latch Configurable Flip-flops ̶ Global and Individual Register Control Signals ̶ Global and Individual Output Enable ̶ Programmable Output Slew Rate ̶ Programmable Output Open Collector Option ̶ Maximum Logic Utilization by Burying a Register with a Output
- Advanced Power Management Features
̶ Automatic μA Standby for “L” Version ̶ Pin-controlled 1m A Standby Mode ̶ Programmable Pin-keeper Circuits on Inputs and I/Os ̶ Reduced-power Feature per Macrocell
- Available in mercial and Industrial...
