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A54SX32 - SX Family FPGAs

This page provides the datasheet information for the A54SX32, a member of the A54SX08 SX Family FPGAs family.

Datasheet Summary

Description

1-1 SX Family Architecture

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Features

  • 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utilization with 100% Pin Locking 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Silicon Explorer II Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Secure Programming Technology P.

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Datasheet preview – A54SX32

Datasheet Details

Part number A54SX32
Manufacturer Actel
File Size 546.42 KB
Description SX Family FPGAs
Datasheet download datasheet A54SX32 Datasheet
Additional preview pages of the A54SX32 datasheet.

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Full PDF Text Transcription

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v3.2 SX Family FPGAs u e ™ Leading Edge Performance • • • • 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew Features • • • • • • • • • • 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utilization with 100% Pin Locking 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Silicon Explorer II Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Secure Programming Technology Prevents Reverse Engineering and Design Theft Specifications • • • • 12,000 to 48,000 System Gates Up to 249 User-Programmable I/O Pins Up to 1,080 Flip-Flops 0.
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