Datasheet Summary
v3.2
SX Family FPGAs u e
™
Leading Edge Performance
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- - 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew
Features
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- - 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utilization with 100% Pin Locking 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Silicon Explorer II Boundary Scan Testing in pliance with IEEE Standard 1149.1 (JTAG) Secure Programming Technology Prevents Reverse Engineering and Design Theft
Specifications
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- - 12,000 to 48,000 System Gates Up to...