A54SX32 Overview
v3.2 SX Family FPGAs u e ™ Leading Edge Performance 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew.
A54SX32 Key Features
- 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utilization with 100% Pin Locking 3.3 V and 5.0
- 12,000 to 48,000 System Gates Up to 249 User-Programmable I/O Pins Up to 1,080 Flip-Flops 0.35 µ CMOS
- 144 A54SX16 16,000 24,000 1,452 924 528 175 3 Yes
- 3.9 ns 0.5 ns Std, -1, -2, -3 C, I, M
- 208 100 176
- 208 100 144, 176
- A54SX32 32,000 48,000 2,880 1,800 1,080 249 3 Yes
- 4.6 ns 0.1 ns Std, -1, -2, -3 C, I, M
- 144, 176 313, 329
- June 2006 © 2006 Actel Corporation