A54SXxx Datasheet - Actel

A54SXxx FPGAs

v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Set-Up 0.25 ns Clock Skew Sp e ci f ic at ion s 66 MHz PCI CPLD and FPGA Integration Single Chip Solution 100% Resource Utilization with 100% Pin Locking 3.3V Operation with 5.0V Input Tolerance Very Low Power Consumption Deterministic, U.

A54SXxx Features

* a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time to market for performance-

A54SXxx_Actel.pdf