AS4C256M16D3LB-12BAN Datasheet - Alliance Semiconductor

AS4C256M16D3LB-12BAN 4Gb DRAM

Pin CK, CK CKE CS ODT RAS, CAS, WE DM (DMU), (DML) Type Input Input Input Input Input Input Function Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referen.

AS4C256M16D3LB-12BAN Revision History 4Gb AS4C256M16D3LB - 12BAN 96 ball FBGA PACKAGE Revision Details Rev 1.0 Preliminary datasheet Date Mar. 2018 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/46 - Rev.1.0 Mar 2018 AS4C256M16D3LB-12BAN Specifications - Density : 4G bits - Organization : 32M words x 16 bits x 8 banks - Package : -.

AS4C256M16D3LB-12BAN Features

* - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-alig

AS4C256M16D3LB-12BAN Datasheet (1.88 MB)