* - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-alig
AS4C256M16D3LB-12BAN Datasheet (1.88 MB)
AS4C256M16D3LB-12BAN
Alliance Semiconductor
1.88 MB
4gb dram.
AS4C256M16D3LB-12BAN Revision History 4Gb AS4C256M16D3LB - 12BAN 96 ball FBGA PACKAGE Revision Details Rev 1.0 Preliminary datasheet Date Mar. 2018 .
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