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AS4C32M16D2C-25BCN 32M x 16 bit DDRII Synchronous DRAM

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Description

AS4C32M16D2C-25BCN AS4C32M16D2C-25BIN Revision History 512M DDR2 AS4C32M16D2C Revision Details Rev 1.0 Initial release 84ball FBGA PACKAGE Date June.

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Features

* JEDEC Standard Compliant
* JEDEC Standard 1.8V I/O (SSTL_18-compatible)
* Power supplies: VDD & VDDQ = +1.8V 0.1V
* Operating temperature: TC = 0~85°C (Commercial) TC = -40~95°C (Industrial)
* Supports JEDEC clock jitter specification
* Fully synchronous operation
* Fa

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AS4C32M16D2C-25BCN 32M bit DDRII Synchronous DRAM Alliance Semiconductor
Alliance Semiconductor AS4C32M16D2C-25BCN-like datasheet
AS4C32M16D2C-25BIN
AS4C32M16D2
AS4C32M16D2A-25BAN
AS4C32M16D2A-25BCN
AS4C32M16D2A-25BIN