Description
April 2003, ver.1.2 ® Cyclone FPGA Family Data Sheet Introduction Preliminary Information .
Logic Array Blocks6 Logic Elements 9 MultiTrack Interconnect 17 Embedded Memory23 Global Clock Network & Phase-Locked Loops34 I/O Structure 44 Power.
Features
* The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to m
Applications
* Cyclone devices support various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to con