Datasheet4U Logo Datasheet4U.com

EP1810

EPLD

EP1810 Features

* Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz s 24 t

EP1810 General Description

The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet. Classic devices support 100% TTL emulation and can easily integrate multiple.

EP1810 Datasheet (657.80 KB)

Preview of EP1810 PDF

Datasheet Details

Part number:

EP1810

Manufacturer:

Altera

File Size:

657.80 KB

Description:

Epld.

📁 Related Datasheet

EP1810EPLD COMPLEX-EPLD 48-CELL 20NS PROP DELAY (Altera)

EP1800 48-Macrocell EPLD (Altera)

EP1 Twin relay for motor and solenoid reversible control (NEC)

EP1-3G1 Twin relay for motor and solenoid reversible control (NEC)

EP1-3G1S Twin relay for motor and solenoid reversible control (NEC)

EP1-3G2 Twin relay for motor and solenoid reversible control (NEC)

EP1-3G2S Twin relay for motor and solenoid reversible control (NEC)

EP1-3G3 Twin relay for motor and solenoid reversible control (NEC)

EP1-3G3S Twin relay for motor and solenoid reversible control (NEC)

EP1-3G4 Twin relay for motor and solenoid reversible control (NEC)

TAGS

EP1810 EPLD Altera

Image Gallery

EP1810 Datasheet Preview Page 2 EP1810 Datasheet Preview Page 3

EP1810 Distributor