EPLD Datasheet | Specifications & PDF Download

USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C344B 32-Macrocell MAX® EPLD Features • High-performance, high-density replacement for TTL, 74HC, and custom

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fax id: 61071CY7C342B CY7C342B Features • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array

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1CY 7C33 5 fax id: 6018 CY7C335 www.DataSheet4U.com Universal Synchronous EPLD Features • 100-MHz output registered operation • Twelve I/O macrocel

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May 1999, ver. 5 Features Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s

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E PL D CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-

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USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 128-Macrocell MAX® EPLD Features • 128 macrocells in eight logic array blocks (LABs) • 20 dedicated inp

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USE ULTRA37000™ FOR ALL NEW DESIGNS CY7C341B 192-Macrocell MAX® EPLD Features • 192 macrocells in 12 logic array blocks (LABs) • Eight dedicated inp

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www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com www.DataSheet4U.com www

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fax id: 61021CY7C343B Features • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array • 0.8-

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fax id: 61021CY7C343B Features • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array • 0.8-

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May 1999, ver. 5 Features Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s

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Features • High-density, High-performance Electrically-erasable Complex Programmable Logic Device – 44-pin, 32 I/O CPLD – 7.5 ns Maximum Pin-to-pin De

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Features • High-density, High-performance Electrically-erasable Complex Programmable Logic Device – 44-pin, 32 I/O CPLD – 7.5 ns Maximum Pin-to-pin De

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® XC7300 CMOS EPLD Family Product Description Features • High-performance Erasable Programmable Logic Devices (EPLDs) – 5 / 7.5 ns pin-to-pin speeds

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