Description
12 DAC Architecture
General 12 Channel Groups 12 A/ B Reigsters And Gain/Offset Adjustment 13 Load DAC 13 Offset DACs  13 Output Amplifier 14 Transfer Function  14 Reference Selection  14 Calibration 15 AD5372 Calibration Example 15 Reset Function  16
Preliminary Technical Data
Clear Function  16 BUSY and LDAC Functions 16 Power-Down Mode  16 Thermal Monitor Function 16 Toggle Mode 17 Serial Interface  18 SPI Write Mode 18 SPI Readback Mode  19 Register Update Rates  19 Channel Addres
Features
- 32-channel DAC in 56-LFCSP and 64-LQFP AD5372 Guaranteed monotonic to 16 bits AD5373 Guaranteed monotonic to 14 bits Maximum output voltage span of 4 × VREF (20 V) Nominal output voltage range of -4 V to +8 V Multiple, independent output spans available System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Thermal Monitoring Function DSP/microcontroller-compatible serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels
DVCC VDD VSS.