AD9531 Datasheet - Analog Devices

AD9531 3-Channel Clock Generator

The AD9531 provides a multioutput clock generator function and three on-chip phase-locked loop (PLL) cores with SPI programmable output frequencies and formats. PLL1 provides two reference inputs and 10 outputs and includes four user selectable loop configurations. The PLL has a fully integrated loo.

AD9531 Features

* 3 fully integrated PLL/VCO cores (PLL1, PLL2, and PLL3) Jitter performance: 0.462 ps rms typical PLL1, fractional-N mode, 12 kHz to 20 MHz bandwidth Loss of reference and lock detection for each PLL Pin-configurable common frequency translations Automatic synchronization of all outputs on power-up M

AD9531-AnalogDevices.pdf