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FEATURES
300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit D/A converters Ultrahigh speed comparator, 3 ps rms jitter Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT 4× to 20× programmable reference clock multiplier Dual 48-bit programmable frequency registers Dual 14-bit programmable phase offset registers 12-bit programmable amplitude modulation and on/off
output shaped keying function Single-pin FSK and BPSK data interfaces PSK capability via I/O interface Linear or nonlinear FM chirp functions with single pin
frequency hold function
CMOS 300 MSPS Complete DDS
AD9852
Frequency ramped FSK <25 ps rms total jitter in clock generator mode Automatic bidirectional frequency sweeping Sin(x)/x correction Simplified control interface
10 MHz
AD9852 Datasheet
