* DC - 4 GHz -170 dBc/Hz floor @ 100 MHz output -164 dBc/Hz floor @ 2 GHz output Integrated Jitter 35 fsRMS@ 100 MHz output 13 fsRMS(calculated) @ 2 GHz output Adjustable output phase with soft/hard reset sync Adjustable output delay in 60 steps of 20 ps Flexible Input Interface: LVPECL,LVDS,CML,CMOS
HMC988LP3E Datasheet (1.26 MB)
HMC988LP3E
1.26 MB
Programmable clock divider/delay.
Clock Distribution - SMT
HMC988LP3E
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz
Typical Applications
The HMC988LP3E is ideal for:
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