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HMC988LP3E PROGRAMMABLE CLOCK DIVIDER/DELAY

HMC988LP3E Description

Clock Distribution - SMT HMC988LP3E v04.1014 PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Typical Applications The HMC988LP3E is ideal for: <.
The HMC988LP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32.

HMC988LP3E Features

* DC - 4 GHz -170 dBc/Hz floor @ 100 MHz output -164 dBc/Hz floor @ 2 GHz output Integrated Jitter 35 fsRMS@ 100 MHz output 13 fsRMS(calculated) @ 2 GHz output Adjustable output phase with soft/hard reset sync Adjustable output delay in 60 steps of 20 ps Flexible Input Interface: LVPECL,LVDS,CML,CMOS

HMC988LP3E Applications

* The HMC988LP3E is ideal for:
* Basestation Digital Pre-Distortion Paths(DPD)
* High Performance Automated Test Equipment(ATE)
* Backplane clock skew management
* Phase Coherence of multiple clock paths
* Clock Delay management to improve setup & hold time marg

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PROGRAMMABLE CLOCK DIVIDER DELAY Analog Devices
Analog Devices HMC988LP3E-like datasheet