* Synchronous Operation in relation to the input Clock DQc DQc
* 2 Stage Registers resulting in Pipeline operation DQc DQc
* On chip address counter (base +3) for Burst operations VSSQ VDDQ
* Self-Timed Write Cycles DQc DQc
* On-Chip Address and Control Regist
AS5SP256K36DQ Datasheet (399.70 KB)
AS5SP256K36DQ
Austin Semiconductor
399.70 KB
Plastic encapsulated microcircuit 9.0mb.
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DQPc DQc DQc VDDQ VSSQ
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9.0Mb, 256K x 36, Synchronous SRAM Pipeline B.
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