AS5SP512K36

Synchronous SRAM

Micross

*  Synchronous Operation in relation to the input Clock

*  2 Stage Registers resulting in Pipeline operation

*  On chip address counter (base +3) for Burst operations

*  Self-Timed Write Cycles

*  On-Chip Address and Control Registers

*  Byte Write support

*  Global Write

AS5SP512K36

Micross

586.07 KB

Synchronous sram.

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AS5SP512K36 Synchronous SRAM Micross

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