CY2PD817 - PECL/CMOS Buffer
The CY2PD817 is a low-voltage LVPECL-to-LVPECL and LVCMOS fanout buffer designed for servers, data communications, and clock management.
The CY2PD817 is ideal for applications requiring mixed differential and single-ended clock distribution.
This device accepts an LVPECL input reference clock and pr
CY2PD817 Features
* DC to 320-MHz operation 50-ps output-output skew 30-ps cycle-cycle jitter 2.5V power supply LVPECL input @ 320-MHz Operation One LVPECL output @ 320-MHz Operation Four LV
