CY2SSTU877 - 10-Output JEDEC-Compliant Zero Delay Buffer

Cypress Semiconductor

Datasheet Details

Part number	CY2SSTU877
Manufacturer	Cypress Semiconductor
File Size	253.19 KB
Description	10-Output JEDEC-Compliant Zero Delay Buffer
Datasheet	CY2SSTU877_CypressSemiconductor.pdf

The CY2SSTU877 is a high-performance, low-skew, low-jitter zero delay buffer designed to distribute differential clocks in high-speed applications.

Operating frequency: 125 MHz to 500 MHz.
Supports DDRII SDRAM.
Ten differential outputs from one differential input.
Spread-Spectrum-compatible.
Low jitter (cycle-to-cycle): < 40 ps.
Very low skew: < 40 ps.
Power management control input.
1.8V operation.
Fully JEDEC-compliant.
52-ball BGA and a 40-pin MLF (QFN) This phase-locked loop (PLL) clock buffer is designed for a VDD of 1.8V, an AVDD of 1.8V and dif.

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Published: Feb 23, 2008 |