CY7C141
Features
- True dual-ported memory cells, which allow simultaneous reads of the same memory location
- 1K x 8 organization
- 0.65 micron CMOS for optimum speed and power
- High speed access: 15 ns
- Low operating power: ICC = 110 m A (maximum)
- Fully asynchronous operation
- Automatic power down
- Master CY7C130/130A/CY7C131/131A easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141
- BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on CY7C140/CY7C141
- INT flag for port-to-port munication
- Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC, 52-pin TQFP
- Pb-free packages available
Functional Description
The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141 are high speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/130A/ CY7C131/131A can be used as either a...
