* 72-Mbit density (4M × 18, 2M × 36)
* 550 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for pr
CY7C25702KV18 Datasheet (604.30 KB)
CY7C25702KV18
Cypress Semiconductor
604.30 KB
72-mbit ddr ii+ sram two-word burst architecture.
CY7C25682KV18 CY7C25702KV18
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
72-Mbit DDR II+ SRAM Two-Word Burst Ar.
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