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CY7C25702KV18, CY7C25682KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C25702KV18 Description

CY7C25682KV18 CY7C25702KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit DDR II+ SRAM Two-Word Burst Ar.

CY7C25702KV18 Features

* 72-Mbit density (4M × 18, 2M × 36)
* 550 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for pr

📥 Download Datasheet

This datasheet PDF includes multiple part numbers: CY7C25702KV18, CY7C25682KV18. Please refer to the document for exact specifications by model.
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Datasheet Details

Part number
CY7C25702KV18, CY7C25682KV18
Manufacturer
Cypress Semiconductor
File Size
604.30 KB
Datasheet
CY7C25682KV18-CypressSemiconductor.pdf
Description
72-Mbit DDR II+ SRAM Two-Word Burst Architecture
Note
This datasheet PDF includes multiple part numbers: CY7C25702KV18, CY7C25682KV18.
Please refer to the document for exact specifications by model.

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📌 All Tags

72-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor
Cypress Semiconductor CY7C25702KV18-like datasheet