CY7C25702KV18 - 72-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C25702KV18 Features
* 72-Mbit density (4M × 18, 2M × 36)
* 550 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for pr
