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CY7C2670KV18 - 144-Mbit DDR II+ SRAM Two-Word Burst Architecture

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Cypress Semiconductor

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CY7C2670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture by Cypress Semiconductor - Datasheet Preview — Datasheet preview – CY7C2670KV18

Datasheet Details

Part number	CY7C2670KV18
Manufacturer	Cypress Semiconductor
File Size	585.49 KB
Description	144-Mbit DDR II+ SRAM Two-Word Burst Architecture
Datasheet	CY7C2670KV18 Datasheet
Additional preview pages of the CY7C2670KV18 datasheet.

Product details

Features

144-Mbit density (4 M × 36).
550-MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.
Data valid pin (QVLD) to indicate valid data on the output.
On-die term.

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Published: Mar 14, 2017 |