S70KL1281 - Self-Refresh DRAM
5 2.
Product Overview 8 3.
Signal Descriptions 9 3.1 Input/Output Summary 9 3.2 Command/Address Bit Assignments 10 3.3 Read Transactions 14 3.4 Write Transactions with Initial Latency (Memory Core Write) 15 3.5 Write Transactions without Initial Latency (Register Write) 17 4.
Memory Space 18 5.
Not Recommended for New Designs (NRND) S27KL0641/S27KS0641 S70KL1281/S70KS1281 3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM 3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB), HyperRAM™ Self-Refresh DRAM Distinctive Characteristics HyperRAM™ Low Signal Count Interface 3.0 V I/O, 11 bus signals Single ended clock (CK) 1.8 V I/O, 12 bus signals Differential clock (CK, CK#) Chip Select (CS#) 8-bit data bus (DQ[7:0]) Read-Write Data Strobe (
