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CY2PD817 PECL/CMOS Buffer

CY2PD817 Description

www.DataSheet4U.com CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer .
The CY2PD817 is a low-voltage LVPECL-to-LVPECL and LVCMOS fanout buffer designed for servers, data communications, and clock management.

CY2PD817 Features

* DC to 320-MHz operation 50-ps output-output skew 30-ps cycle-cycle jitter 2.5V power supply LVPECL input @ 320-MHz Operation One LVPECL output @ 320-MHz Operation Four LV

CY2PD817 Applications

* requiring mixed differential and single-ended clock distribution. This device accepts an LVPECL input reference clock and provides one LVPECL and six LVCMOS/LVTTL output clocks. The outputs are partitioned into three banks of one, two, and four outputs. The LVPECL output is a buffered copy of the in

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Cypress Semiconductor CY2PD817-like datasheet