Description
W161
CPU Clock Outputs 0 through 2: CPU clock outputs.Their output voltage swing is controlled by voltage applied to VDDQ2. PCI Clock Outputs 0 through 9: Output voltage swing is controlled by voltage applied to VDDQ3. CPU-Divide-By-2 Output: This serves as a reference input signal for Direct Rambus Clock Generator (Cypress W134).The output voltage is determined by VDDQ2. 66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by voltage applied to VDDQ3. I/O APIC Clock Output:
Features
- Maximized EMI Suppression using Cypress’s Spread Spectrum Technology.
- Three copies of CPU outputs at 100 or 133 MHz.
- Three copies of 66-MHz output at 3.3V.
- Ten copies of PCI clocks at 33 MHz, 3.3V.
- Two copies of 14.318-MHz reference output at 3.3V.
- One copy of 48-MHz USB clock.
- One copy of CPU-divide-by-2 output as reference input to Direct Rambus™ Clock Generator (Cypress W134).
- Available in 48-pin SSOP (300 mils) Spread S.
W161_CypressSemiconductor.pdf
