DTC34LR86L - +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver
The D TC34LF86L/LR86L rec eivers co nvert the L VDS (Low Voltage Differential Signaling) data streams back into 28 bit s of CMOS/ TTL dat a with falling edge (DTC34LF86L) or risin g edge (DTC34LR86L) clock for convenient int erface with a variet y of L CD p anel controllers.
A phase-locked transmit
DTC34LR86L Features
* ▓ Wide frequency range : 20 to 85 MHz shift clock support Narrow bus (10 lines) reduces cable size ▓ Sing le 3.3V supply ▓ Po wer-Down Mode ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and SXGA Up to 297.5 Megabytes/sec bandwidth Up to 2.38 Gbps throughput 3
