DS1350AB Datasheet (Dallas Semiconductor)

DS1350AB, 4096k Nonvolatile SRAM

A0 - A18 DQ0 - DQ7 CE WE OE RST BW VCC GND NC - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Reset Output - Battery Warning - Power (+5V) - Ground - No Connect DESCRIPTION The DS1350 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs org

DS1350AB Features

* 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Power supply monitor resets processor when VCC power loss occurs and holds processor in reset during VCC ramp-up Battery monitor checks remaining capacity daily Read and write access ti