M15T2G16128A Datasheet - ESMT

M15T2G16128A, DDR3 SDRAM

ESMT DDR3(L) SDRAM

Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

M15T2G16128A-ESMT.pdf