M15T2G16128A - DDR3 SDRAM

Datasheet Summary

The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices.

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration 128Mb x16 # of Bank 8.

ESMT

Part number	M15T2G16128A
Manufacturer	ESMT
File Size	3.85 MB
Description	DDR3 SDRAM
Datasheet	M15T2G16128A Datasheet
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ESMT DDR3(L) SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.

Published: Sep 20, 2018 |