M55D4G32128A-EEBG2R - 16M x 32 Bit x 8 Banks LPDDR3 SDRAM
Ball Name Type CK_t, CK_c Input CKE Input CS_n CA[n:0] DQ[n:0] Input Input I/O DQS[n:0]_t, I/O DQS[n:0]_c DM[n:0] Input ODT Input M55D4G32128A (2R) Function Clock: CK_t and CK_c are differential clock inputs.
All Double Data Rate (DDR) CA inputs are sampled on both positive and negati
