4X16E83V Datasheet - ETC

4X16E83V 4 MEG x 16 EDO DRAM

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 co.

4X16E83V Features

* Single +3.3V ±0.3V power supply

* Industry-standard x16 pinout, timing, functions, and package

* 12 row, 10 column addresses (4) 13 row, 9 column addresses (8)

* High-performance CMOS silicon-gate process

* All inputs, outputs and clocks are LVTTL-compatible

4X16E83V_ETC.pdf