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AR2010 Datasheet - ETC

AR2010 GPS Controller SoC

The wireless communication solution provider GPS Controller SoC AR2010 The AR2010 GPS controller SoC is a single chip integrated processor with peripherals suitable for all GPS receiver related products, GPS engine board, GPS mouse, GPS CF-card, GPS watch, GPS handheld navigator/locator, PDA with GPS receiver, add-on notebook PC and other specific designs. www.DataSheet4U.com Ar2010 Block Diagram Async SRAM/ Mask ROM/ Flash ROM SDRAM GPS RF Front-end GPS Decoder RTC/ Timer UART x2 SDRAM C.

AR2010 Features

* The AR2010 controller SoC includes the following functions and capabilities: CPU: MIPS 1 class R3000 level, 32-bit RISC processor with 2 KB Instruction cache and 2 KB data cache, and up to 100 MHz CPU Clock rate Built-in 64 KB SRAM SDRAM Controller supports two SDRAM banks of 16-bit data bus Up to

AR2010 Datasheet (529.40 KB)