QL2007 Datasheet - ETC

QL2007, pASIC 2 FPGA Combining Speed

www.DataSheet4U.com 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev.E pASIC 2 HIGHLIGHTS ® QL2007 Ultimate Veri.
Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clo.

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QL2007_ETC.pdf

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Datasheet Details

Part number:

QL2007

Manufacturer:

ETC

File Size:

331.88 KB

Description:

pASIC 2 FPGA Combining Speed

Features

* -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2007 Block Diagram 480 Logic Cells 3-25 DataSheet 4 U . com www. DataS

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QL2007 pASIC FPGA Combining Speed ETC

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