QL2007 Datasheet - ETC

QL2007 pASIC 2 FPGA Combining Speed

Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-d.

www.DataSheet4U.com 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. E pASIC 2 HIGHLIGHTS ® QL2007 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device … 7,000 usable ASICgates, 174 I/O pins -16-bit counter speeds exceeding 200 MHz -7,0.

QL2007 Features

* -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2007 Block Diagram 480 Logic Cells 3-25 DataSheet 4 U .com www.DataS

QL2007_ETC.pdf

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Datasheet Details

Part number:

QL2007

Manufacturer:

ETC

File Size:

331.88 KB

Description:

Pasic 2 fpga combining speed.

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