www.DataSheet4U.com 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev.
E pASIC 2 HIGHLIGHTS ® QL2007 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device … 7,000 usable ASICgates, 174 I/O pins -16-bit counter speeds exceeding 200 MHz -7,0